URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] - Rev 12

Rev	Log message	Author	Age	Path
11	Updated bridge example to fix a number of small bugs. First packet now exits bridge from all ports.	ghutchis	5416d 08h	/srdydrdy_lib/trunk/rtl/verilog/
10	Fixed "locked" variable in rrslow	ghutchis	5416d 12h	/srdydrdy_lib/trunk/rtl/verilog/
7	Added rrslow	ghutchis	5420d 04h	/srdydrdy_lib/trunk/rtl/verilog/
6	Modified "B" output buffer for full-rate operation	ghutchis	5422d 13h	/srdydrdy_lib/trunk/rtl/verilog/
3	Added small/synchronizer FIFO, along with minimal testbench	ghutchis	5424d 23h	/srdydrdy_lib/trunk/rtl/verilog/
2	Initial commit of directory structure and basic components	ghutchis	5429d 08h	/srdydrdy_lib/trunk/rtl/verilog/