URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] - Rev 17

Rev	Log message	Author	Age	Path
16	Changed fifo head/tail to have separate usage counters for producer and consumer side. Fixed bug in port_ring_tap where it jumped to non-existent state. Changed default dump mode for icarus to lxt.	ghutchis	5268d 08h	/srdydrdy_lib/trunk/rtl/verilog/
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5270d 06h	/srdydrdy_lib/trunk/rtl/verilog/
13	Fixed FIFO Full condition for large fifo, added separate tests to example bridge	ghutchis	5273d 16h	/srdydrdy_lib/trunk/rtl/verilog/
11	Updated bridge example to fix a number of small bugs. First packet now exits bridge from all ports.	ghutchis	5275d 15h	/srdydrdy_lib/trunk/rtl/verilog/
10	Fixed "locked" variable in rrslow	ghutchis	5275d 19h	/srdydrdy_lib/trunk/rtl/verilog/
7	Added rrslow	ghutchis	5279d 11h	/srdydrdy_lib/trunk/rtl/verilog/
6	Modified "B" output buffer for full-rate operation	ghutchis	5281d 20h	/srdydrdy_lib/trunk/rtl/verilog/
3	Added small/synchronizer FIFO, along with minimal testbench	ghutchis	5284d 06h	/srdydrdy_lib/trunk/rtl/verilog/
2	Initial commit of directory structure and basic components	ghutchis	5288d 15h	/srdydrdy_lib/trunk/rtl/verilog/