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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] - Rev 29

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Rev	Log message	Author	Age	Path
29	Updated arbitration	ghutchis	4880d 08h	/srdydrdy_lib/trunk/rtl/verilog/
28	Added ports & fixed signal propagation	ghutchis	4985d 08h	/srdydrdy_lib/trunk/rtl/verilog/
26	Added backpressure drop module	ghutchis	4986d 01h	/srdydrdy_lib/trunk/rtl/verilog/
25	Added sd_sync component for cross-clock synchronization	ghutchis	5091d 23h	/srdydrdy_lib/trunk/rtl/verilog/
24	Added CRC32 checker to environment & RTL	ghutchis	5209d 00h	/srdydrdy_lib/trunk/rtl/verilog/
22	Created separate module-level environments for fifo_b and scoreboard. Added some documentation on the example bridge, including a PDF preso giving a basic introduction to ethernet.	ghutchis	5405d 03h	/srdydrdy_lib/trunk/rtl/verilog/
21	Changed rrslow to rrmux, updated descriptions, changed bridge mux to fast arb	ghutchis	5406d 05h	/srdydrdy_lib/trunk/rtl/verilog/
20	Added fast arb mode	ghutchis	5406d 07h	/srdydrdy_lib/trunk/rtl/verilog/
19	Fixed several minor bugs in scoreboard, adjusted usage width in sd_fifo_b, and updated component documentation.	ghutchis	5406d 19h	/srdydrdy_lib/trunk/rtl/verilog/
18	Added scoreboard and scoreboard testbench	ghutchis	5406d 23h	/srdydrdy_lib/trunk/rtl/verilog/
16	Changed fifo head/tail to have separate usage counters for producer and consumer side. Fixed bug in port_ring_tap where it jumped to non-existent state. Changed default dump mode for icarus to lxt.	ghutchis	5407d 20h	/srdydrdy_lib/trunk/rtl/verilog/
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5409d 18h	/srdydrdy_lib/trunk/rtl/verilog/
13	Fixed FIFO Full condition for large fifo, added separate tests to example bridge	ghutchis	5413d 04h	/srdydrdy_lib/trunk/rtl/verilog/
11	Updated bridge example to fix a number of small bugs. First packet now exits bridge from all ports.	ghutchis	5415d 03h	/srdydrdy_lib/trunk/rtl/verilog/
10	Fixed "locked" variable in rrslow	ghutchis	5415d 07h	/srdydrdy_lib/trunk/rtl/verilog/
7	Added rrslow	ghutchis	5418d 23h	/srdydrdy_lib/trunk/rtl/verilog/
6	Modified "B" output buffer for full-rate operation	ghutchis	5421d 08h	/srdydrdy_lib/trunk/rtl/verilog/
3	Added small/synchronizer FIFO, along with minimal testbench	ghutchis	5423d 17h	/srdydrdy_lib/trunk/rtl/verilog/
2	Initial commit of directory structure and basic components	ghutchis	5428d 03h	/srdydrdy_lib/trunk/rtl/verilog/

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