URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] - Rev 17

Rev	Log message	Author	Age	Path
16	Changed fifo head/tail to have separate usage counters for producer and consumer side. Fixed bug in port_ring_tap where it jumped to non-existent state. Changed default dump mode for icarus to lxt.	ghutchis	5410d 06h	/srdydrdy_lib/trunk/rtl/verilog/buffers/
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5412d 04h	/srdydrdy_lib/trunk/rtl/verilog/buffers/
13	Fixed FIFO Full condition for large fifo, added separate tests to example bridge	ghutchis	5415d 15h	/srdydrdy_lib/trunk/rtl/verilog/buffers/
11	Updated bridge example to fix a number of small bugs. First packet now exits bridge from all ports.	ghutchis	5417d 13h	/srdydrdy_lib/trunk/rtl/verilog/buffers/
6	Modified "B" output buffer for full-rate operation	ghutchis	5423d 18h	/srdydrdy_lib/trunk/rtl/verilog/buffers/
3	Added small/synchronizer FIFO, along with minimal testbench	ghutchis	5426d 04h	/srdydrdy_lib/trunk/rtl/verilog/buffers/
2	Initial commit of directory structure and basic components	ghutchis	5430d 13h	/srdydrdy_lib/trunk/rtl/verilog/buffers/