URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks/] - Rev 30

Rev	Log message	Author	Age	Path
30	Added llmanager component	ghutchis	4445d 21h	/srdydrdy_lib/trunk/rtl/verilog/forks/
29	Updated arbitration	ghutchis	4760d 21h	/srdydrdy_lib/trunk/rtl/verilog/forks/
24	Added CRC32 checker to environment & RTL	ghutchis	5089d 12h	/srdydrdy_lib/trunk/rtl/verilog/forks/
21	Changed rrslow to rrmux, updated descriptions, changed bridge mux to fast arb	ghutchis	5286d 18h	/srdydrdy_lib/trunk/rtl/verilog/forks/
20	Added fast arb mode	ghutchis	5286d 20h	/srdydrdy_lib/trunk/rtl/verilog/forks/
18	Added scoreboard and scoreboard testbench	ghutchis	5287d 12h	/srdydrdy_lib/trunk/rtl/verilog/forks/
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5290d 07h	/srdydrdy_lib/trunk/rtl/verilog/forks/
10	Fixed "locked" variable in rrslow	ghutchis	5295d 20h	/srdydrdy_lib/trunk/rtl/verilog/forks/
7	Added rrslow	ghutchis	5299d 12h	/srdydrdy_lib/trunk/rtl/verilog/forks/
2	Initial commit of directory structure and basic components	ghutchis	5308d 16h	/srdydrdy_lib/trunk/rtl/verilog/forks/