URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks/] - Rev 17

Rev	Log message	Author	Age	Path
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5412d 04h	/srdydrdy_lib/trunk/rtl/verilog/forks/
10	Fixed "locked" variable in rrslow	ghutchis	5417d 18h	/srdydrdy_lib/trunk/rtl/verilog/forks/
7	Added rrslow	ghutchis	5421d 10h	/srdydrdy_lib/trunk/rtl/verilog/forks/
2	Initial commit of directory structure and basic components	ghutchis	5430d 13h	/srdydrdy_lib/trunk/rtl/verilog/forks/