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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks/] - Rev 22

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Rev Log message Author Age Path
21 Changed rrslow to rrmux, updated descriptions, changed
bridge mux to fast arb
ghutchis 5312d 00h /srdydrdy_lib/trunk/rtl/verilog/forks/
20 Added fast arb mode ghutchis 5312d 02h /srdydrdy_lib/trunk/rtl/verilog/forks/
18 Added scoreboard and scoreboard testbench ghutchis 5312d 18h /srdydrdy_lib/trunk/rtl/verilog/forks/
14 - Modified large FIFO to remove "full" signal and store only N-1 words
- changed small FIFO to use memory instance instead of registers
- changed sequence generator to enable more complex tests
- changed sd_mirror to use combinatorial assign output
ghutchis 5315d 13h /srdydrdy_lib/trunk/rtl/verilog/forks/
10 Fixed "locked" variable in rrslow ghutchis 5321d 02h /srdydrdy_lib/trunk/rtl/verilog/forks/
7 Added rrslow ghutchis 5324d 18h /srdydrdy_lib/trunk/rtl/verilog/forks/
2 Initial commit of directory structure and basic components ghutchis 5333d 22h /srdydrdy_lib/trunk/rtl/verilog/forks/

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