URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [utility/] - Rev 30

Rev	Log message	Author	Age	Path
30	Added llmanager component	ghutchis	4449d 22h	/srdydrdy_lib/trunk/rtl/verilog/utility/
28	Added ports & fixed signal propagation	ghutchis	4869d 21h	/srdydrdy_lib/trunk/rtl/verilog/utility/
26	Added backpressure drop module	ghutchis	4870d 14h	/srdydrdy_lib/trunk/rtl/verilog/utility/
25	Added sd_sync component for cross-clock synchronization	ghutchis	4976d 12h	/srdydrdy_lib/trunk/rtl/verilog/utility/
24	Added CRC32 checker to environment & RTL	ghutchis	5093d 13h	/srdydrdy_lib/trunk/rtl/verilog/utility/
19	Fixed several minor bugs in scoreboard, adjusted usage width in sd_fifo_b, and updated component documentation.	ghutchis	5291d 08h	/srdydrdy_lib/trunk/rtl/verilog/utility/
18	Added scoreboard and scoreboard testbench	ghutchis	5291d 12h	/srdydrdy_lib/trunk/rtl/verilog/utility/