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[/] [storm_core/] - Rev 18

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Rev Log message Author Age Path
18 makefile update to ensure no thumb code is generated zero_gravity 4515d 20h /storm_core/
17 small synthesis-friendly update of memory components zero_gravity 4518d 13h /storm_core/
16 WB_TGC(5) signal fixed (indicating instruction/data fetch),
coprocessor read-access bug fixed		 zero_gravity 4518d 15h /storm_core/
15 new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;) zero_gravity 4518d 20h /storm_core/
14 - corrected stupid error in access arbiter
- updated minor issues		 zero_gravity 4656d 16h /storm_core/
13 - corrected endianess converter for memory access
- corrected error in temporal dependence detector		 zero_gravity 4657d 12h /storm_core/
12 - corrected error in memory write back interface
- corrected immediate/register offset for byte/halfword memory access		 zero_gravity 4657d 17h /storm_core/
11 zero_gravity 4660d 21h /storm_core/
10 New CORE version, ncluding complete system setup with inbuilt memory and wishbone interface.
Ready to execute assembled ARM ASM code, arm-elf-assembler included.		 zero_gravity 4660d 21h /storm_core/
9 documentation updated zero_gravity 4750d 19h /storm_core/
8 documentation uploaded ;) zero_gravity 4752d 13h /storm_core/
7 - new register file architecture
- fixed multi-cycle op bug
- architecture update		 zero_gravity 4756d 12h /storm_core/
6 new core version - now with arm compatible memory interface zero_gravity 4762d 12h /storm_core/
5 memory interface updated zero_gravity 4813d 11h /storm_core/
4 new instruction cycle controller - interrupt call bug seems to be fixed zero_gravity 4815d 13h /storm_core/
3 zero_gravity 4816d 20h /storm_core/
2 zero_gravity 4828d 21h /storm_core/
1 The project and the structure was created root 4832d 04h /storm_core/

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