OpenCores
URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

Subversion Repositories storm_core

[/] [storm_core/] - Rev 24

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
24 - changed back to original oc svn folder structure
- bug-fix in documentary
- WB_ERR_I signal added to terminate wishbone bus access
- bug-fix: system mode register set and privs
zero_gravity 4484d 01h /storm_core/
23 zero_gravity 4484d 01h /storm_core/
22 changed back to original svn folder structure zero_gravity 4484d 01h /storm_core/
21 smaller, faster, better ;)
* bug-fix: load-multiple instructions
* new cache-control system
* direct-accessible IO area can be specified
* extended demo implementation
zero_gravity 4490d 20h /storm_core/
20 - update of data sheet -> note for system memory map layout and d-cache configuration zero_gravity 4506d 15h /storm_core/
19 - simulation test bench added
- example for compatible wishbone fabric/SoC added
- block transfers from user bank updated
zero_gravity 4506d 18h /storm_core/
18 makefile update to ensure no thumb code is generated zero_gravity 4511d 23h /storm_core/
17 small synthesis-friendly update of memory components zero_gravity 4514d 17h /storm_core/
16 WB_TGC(5) signal fixed (indicating instruction/data fetch),
coprocessor read-access bug fixed
zero_gravity 4514d 19h /storm_core/
15 new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;) zero_gravity 4514d 23h /storm_core/
14 - corrected stupid error in access arbiter
- updated minor issues
zero_gravity 4652d 19h /storm_core/
13 - corrected endianess converter for memory access
- corrected error in temporal dependence detector
zero_gravity 4653d 15h /storm_core/
12 - corrected error in memory write back interface
- corrected immediate/register offset for byte/halfword memory access
zero_gravity 4653d 21h /storm_core/
11 zero_gravity 4657d 01h /storm_core/
10 New CORE version, ncluding complete system setup with inbuilt memory and wishbone interface.
Ready to execute assembled ARM ASM code, arm-elf-assembler included.
zero_gravity 4657d 01h /storm_core/
9 documentation updated zero_gravity 4746d 23h /storm_core/
8 documentation uploaded ;) zero_gravity 4748d 17h /storm_core/
7 - new register file architecture
- fixed multi-cycle op bug
- architecture update
zero_gravity 4752d 15h /storm_core/
6 new core version - now with arm compatible memory interface zero_gravity 4758d 16h /storm_core/
5 memory interface updated zero_gravity 4809d 14h /storm_core/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.