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Subversion Repositories storm_core

[/] [storm_core/] - Rev 31

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Rev	Log message	Author	Age	Path
31	- small documentary edits - CACHE.vhd modified for better synthesis results - BUS_UNIT.vhd update to fulfill WB specs	zero_gravity	4456d 08h	/storm_core/
30	- minor edits in doc	zero_gravity	4461d 09h	/storm_core/
29	- specific IO area is now auto protected - Wishbone compatibility extended - cache flush optimized - accelerated bus cycles due to less overhead	zero_gravity	4462d 09h	/storm_core/
28	- bugfix in pipeline re-sync of d/i-cache - optimized bus unit - minor edits... ^^	zero_gravity	4473d 12h	/storm_core/
27	updated "sim" folder - error in testbench environment -> old components -> weren't compatible to new core version anymore => FIXED! ;) - thanks to Pratip Mukherjee	zero_gravity	4477d 11h	/storm_core/
26	bug fixes: - change in priority for cache miss/dirty/io_access - memory based pc modifications - removed internal timer	zero_gravity	4478d 11h	/storm_core/
25	bug-fix in cache component: -> error in cache page-access history manager	zero_gravity	4486d 19h	/storm_core/
24	- changed back to original oc svn folder structure - bug-fix in documentary - WB_ERR_I signal added to terminate wishbone bus access - bug-fix: system mode register set and privs	zero_gravity	4487d 18h	/storm_core/
23		zero_gravity	4487d 18h	/storm_core/
22	changed back to original svn folder structure	zero_gravity	4487d 18h	/storm_core/
21	smaller, faster, better ;) * bug-fix: load-multiple instructions * new cache-control system * direct-accessible IO area can be specified * extended demo implementation	zero_gravity	4494d 13h	/storm_core/
20	- update of data sheet -> note for system memory map layout and d-cache configuration	zero_gravity	4510d 08h	/storm_core/
19	- simulation test bench added - example for compatible wishbone fabric/SoC added - block transfers from user bank updated	zero_gravity	4510d 12h	/storm_core/
18	makefile update to ensure no thumb code is generated	zero_gravity	4515d 16h	/storm_core/
17	small synthesis-friendly update of memory components	zero_gravity	4518d 10h	/storm_core/
16	WB_TGC(5) signal fixed (indicating instruction/data fetch), coprocessor read-access bug fixed	zero_gravity	4518d 12h	/storm_core/
15	new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;)	zero_gravity	4518d 16h	/storm_core/
14	- corrected stupid error in access arbiter - updated minor issues	zero_gravity	4656d 13h	/storm_core/
13	- corrected endianess converter for memory access - corrected error in temporal dependence detector	zero_gravity	4657d 08h	/storm_core/
12	- corrected error in memory write back interface - corrected immediate/register offset for byte/halfword memory access	zero_gravity	4657d 14h	/storm_core/

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Subversion Repositories storm_core

[/] [storm_core/] - Rev 31

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