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[/] [t400/] [trunk/] [rtl/] [vhdl/] - Rev 49

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Rev Log message Author Age Path
49 io_in added arniml 6607d 18h /t400/trunk/rtl/vhdl/
48 instructions ININ and INIL implemented arniml 6607d 18h /t400/trunk/rtl/vhdl/
47 simplify ININ/INIL instruction support arniml 6607d 18h /t400/trunk/rtl/vhdl/
46 operations for IN port added arniml 6607d 18h /t400/trunk/rtl/vhdl/
45 initial check-in arniml 6607d 18h /t400/trunk/rtl/vhdl/
43 route cko to ALU for INIL instruction arniml 6607d 20h /t400/trunk/rtl/vhdl/
39 select CK divide by 8 arniml 6609d 15h /t400/trunk/rtl/vhdl/
37 timer module included arniml 6609d 15h /t400/trunk/rtl/vhdl/
36 skip-on-timer implemented arniml 6609d 15h /t400/trunk/rtl/vhdl/
35 initial check-in arniml 6609d 15h /t400/trunk/rtl/vhdl/
27 connect missing input direction for IO G arniml 6612d 17h /t400/trunk/rtl/vhdl/
15 initial check-in arniml 6614d 19h /t400/trunk/rtl/vhdl/
14 t420 hierarchies added arniml 6614d 19h /t400/trunk/rtl/vhdl/
13 hand-down clock divider option arniml 6621d 15h /t400/trunk/rtl/vhdl/
12 fix sensitivity list arniml 6622d 16h /t400/trunk/rtl/vhdl/
10 renamed t400_por configuration to rtl arniml 6622d 16h /t400/trunk/rtl/vhdl/
8 phi1_en_q is dedicated enable for PHI1 clock to suppress glitches on sk_o arniml 6623d 04h /t400/trunk/rtl/vhdl/
2 import from local CVS repository, LOC_CVS_0_1 arniml 6623d 16h /t400/trunk/rtl/vhdl/

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