URL https://opencores.org/ocsvn/t400/t400/trunk

Subversion Repositories t400

[/] [t400/] [trunk/] [rtl/] [vhdl/] - Rev 53

Rev	Log message	Author	Age	Path
53	use to_X01 for G input	arniml	6592d 03h	/t400/trunk/rtl/vhdl/
52	+ reset neg_edge flip-flops to '1' -> after por, a 1-to-0 edge is required to trigger the latches initially + use to_X01	arniml	6592d 04h	/t400/trunk/rtl/vhdl/
49	io_in added	arniml	6593d 05h	/t400/trunk/rtl/vhdl/
48	instructions ININ and INIL implemented	arniml	6593d 05h	/t400/trunk/rtl/vhdl/
47	simplify ININ/INIL instruction support	arniml	6593d 05h	/t400/trunk/rtl/vhdl/
46	operations for IN port added	arniml	6593d 05h	/t400/trunk/rtl/vhdl/
45	initial check-in	arniml	6593d 05h	/t400/trunk/rtl/vhdl/
43	route cko to ALU for INIL instruction	arniml	6593d 07h	/t400/trunk/rtl/vhdl/
39	select CK divide by 8	arniml	6595d 02h	/t400/trunk/rtl/vhdl/
37	timer module included	arniml	6595d 02h	/t400/trunk/rtl/vhdl/
36	skip-on-timer implemented	arniml	6595d 02h	/t400/trunk/rtl/vhdl/
35	initial check-in	arniml	6595d 02h	/t400/trunk/rtl/vhdl/
27	connect missing input direction for IO G	arniml	6598d 04h	/t400/trunk/rtl/vhdl/
15	initial check-in	arniml	6600d 06h	/t400/trunk/rtl/vhdl/
14	t420 hierarchies added	arniml	6600d 06h	/t400/trunk/rtl/vhdl/
13	hand-down clock divider option	arniml	6607d 02h	/t400/trunk/rtl/vhdl/
12	fix sensitivity list	arniml	6608d 02h	/t400/trunk/rtl/vhdl/
10	renamed t400_por configuration to rtl	arniml	6608d 03h	/t400/trunk/rtl/vhdl/
8	phi1_en_q is dedicated enable for PHI1 clock to suppress glitches on sk_o	arniml	6608d 15h	/t400/trunk/rtl/vhdl/
2	import from local CVS repository, LOC_CVS_0_1	arniml	6609d 03h	/t400/trunk/rtl/vhdl/