URL https://opencores.org/ocsvn/t400/t400/trunk

Subversion Repositories t400

[/] [t400/] [trunk/] [sw/] [verif/] - Rev 42

Rev	Log message	Author	Age	Path
42	add note about INL verification	arniml	6625d 17h	/t400/trunk/sw/verif/
41	initial check-in	arniml	6626d 07h	/t400/trunk/sw/verif/
40	initial check-in	arniml	6626d 17h	/t400/trunk/sw/verif/
35	initial check-in	arniml	6627d 08h	/t400/trunk/sw/verif/
34	initial check-in	arniml	6627d 09h	/t400/trunk/sw/verif/
33	initial check-in	arniml	6628d 10h	/t400/trunk/sw/verif/
32	initial check-in	arniml	6629d 09h	/t400/trunk/sw/verif/
30	adapt for T420 testbench	arniml	6629d 10h	/t400/trunk/sw/verif/
28	adjust G port signalling to current T420 TB implementation	arniml	6630d 10h	/t400/trunk/sw/verif/
26	fix org for page 11 in COP420 code	arniml	6630d 10h	/t400/trunk/sw/verif/
25	fix wrong aisc commands	arniml	6630d 11h	/t400/trunk/sw/verif/
24	finalize test	arniml	6630d 12h	/t400/trunk/sw/verif/
23	finalize test	arniml	6631d 03h	/t400/trunk/sw/verif/
22	finish test	arniml	6631d 11h	/t400/trunk/sw/verif/
17	remove direct specification of cpu type	arniml	6632d 12h	/t400/trunk/sw/verif/
16	enabled t420 support	arniml	6632d 12h	/t400/trunk/sw/verif/
6	initial check-in	arniml	6640d 21h	/t400/trunk/sw/verif/
2	import from local CVS repository, LOC_CVS_0_1	arniml	6641d 09h	/t400/trunk/sw/verif/