URL https://opencores.org/ocsvn/t400/t400/trunk

Subversion Repositories t400

[/] [t400/] [trunk/] [sw/] [verif/] [black_box/] - Rev 42

Rev	Log message	Author	Age	Path
42	add note about INL verification	arniml	6625d 08h	/t400/trunk/sw/verif/black_box/
41	initial check-in	arniml	6625d 23h	/t400/trunk/sw/verif/black_box/
40	initial check-in	arniml	6626d 08h	/t400/trunk/sw/verif/black_box/
35	initial check-in	arniml	6626d 23h	/t400/trunk/sw/verif/black_box/
34	initial check-in	arniml	6627d 00h	/t400/trunk/sw/verif/black_box/
33	initial check-in	arniml	6628d 01h	/t400/trunk/sw/verif/black_box/
32	initial check-in	arniml	6629d 01h	/t400/trunk/sw/verif/black_box/
30	adapt for T420 testbench	arniml	6629d 01h	/t400/trunk/sw/verif/black_box/
28	adjust G port signalling to current T420 TB implementation	arniml	6630d 01h	/t400/trunk/sw/verif/black_box/
26	fix org for page 11 in COP420 code	arniml	6630d 01h	/t400/trunk/sw/verif/black_box/
25	fix wrong aisc commands	arniml	6630d 02h	/t400/trunk/sw/verif/black_box/
24	finalize test	arniml	6630d 03h	/t400/trunk/sw/verif/black_box/
23	finalize test	arniml	6630d 18h	/t400/trunk/sw/verif/black_box/
22	finish test	arniml	6631d 02h	/t400/trunk/sw/verif/black_box/
17	remove direct specification of cpu type	arniml	6632d 03h	/t400/trunk/sw/verif/black_box/
6	initial check-in	arniml	6640d 13h	/t400/trunk/sw/verif/black_box/
2	import from local CVS repository, LOC_CVS_0_1	arniml	6641d 00h	/t400/trunk/sw/verif/black_box/