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[/] [t48/] [tags/] [rel_0_1_beta/] [bench/] [vhdl/] - Rev 292

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5641d 12h	/t48/tags/rel_0_1_beta/bench/vhdl/
251	This commit was manufactured by cvs2svn to create tag 'rel_0_1_beta'.		6611d 20h	/t48/tags/rel_0_1_beta/bench/vhdl/
83	connect if_timing to P2 output of T48	arniml	7421d 01h	/t48/tags/rel_0_1_beta/bench/vhdl/
82	check expander timings	arniml	7421d 01h	/t48/tags/rel_0_1_beta/bench/vhdl/
81	initial check-in	arniml	7421d 05h	/t48/tags/rel_0_1_beta/bench/vhdl/
80	added if_timing	arniml	7421d 05h	/t48/tags/rel_0_1_beta/bench/vhdl/
68	connect T0 and T1 to P1	arniml	7428d 02h	/t48/tags/rel_0_1_beta/bench/vhdl/
67	initial check-in	arniml	7428d 03h	/t48/tags/rel_0_1_beta/bench/vhdl/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7432d 01h	/t48/tags/rel_0_1_beta/bench/vhdl/
33	rename pX_limp to pX_low_imp	arniml	7448d 02h	/t48/tags/rel_0_1_beta/bench/vhdl/
30	connect prog_n_o	arniml	7449d 00h	/t48/tags/rel_0_1_beta/bench/vhdl/
19	enhance simulation result string	arniml	7450d 23h	/t48/tags/rel_0_1_beta/bench/vhdl/
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7452d 22h	/t48/tags/rel_0_1_beta/bench/vhdl/
8	initial check-in	arniml	7453d 00h	/t48/tags/rel_0_1_beta/bench/vhdl/