URL https://opencores.org/ocsvn/t48/t48/trunk

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[/] [t48/] [tags/] [rel_0_1_beta/] [bench/] [vhdl/] - Rev 304

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5591d 23h	/t48/tags/rel_0_1_beta/bench/vhdl/
251	This commit was manufactured by cvs2svn to create tag 'rel_0_1_beta'.		6562d 08h	/t48/tags/rel_0_1_beta/bench/vhdl/
83	connect if_timing to P2 output of T48	arniml	7371d 12h	/t48/tags/rel_0_1_beta/bench/vhdl/
82	check expander timings	arniml	7371d 12h	/t48/tags/rel_0_1_beta/bench/vhdl/
81	initial check-in	arniml	7371d 17h	/t48/tags/rel_0_1_beta/bench/vhdl/
80	added if_timing	arniml	7371d 17h	/t48/tags/rel_0_1_beta/bench/vhdl/
68	connect T0 and T1 to P1	arniml	7378d 14h	/t48/tags/rel_0_1_beta/bench/vhdl/
67	initial check-in	arniml	7378d 14h	/t48/tags/rel_0_1_beta/bench/vhdl/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7382d 12h	/t48/tags/rel_0_1_beta/bench/vhdl/
33	rename pX_limp to pX_low_imp	arniml	7398d 13h	/t48/tags/rel_0_1_beta/bench/vhdl/
30	connect prog_n_o	arniml	7399d 11h	/t48/tags/rel_0_1_beta/bench/vhdl/
19	enhance simulation result string	arniml	7401d 10h	/t48/tags/rel_0_1_beta/bench/vhdl/
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7403d 10h	/t48/tags/rel_0_1_beta/bench/vhdl/
8	initial check-in	arniml	7403d 11h	/t48/tags/rel_0_1_beta/bench/vhdl/