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Rev Log message Author Age Path
292 New directory structure. root 5571d 18h /t48/tags/rel_0_1_beta/sw/
251 This commit was manufactured by cvs2svn to create tag 'rel_0_1_beta'. 6542d 03h /t48/tags/rel_0_1_beta/sw/
88 allow memory bank switching during interrupts arniml 7345d 11h /t48/tags/rel_0_1_beta/sw/
87 abort gracfullt if memory bank switching does not work arniml 7345d 11h /t48/tags/rel_0_1_beta/sw/
85 initial check-in arniml 7345d 16h /t48/tags/rel_0_1_beta/sw/
74 enhance pass/fail detection arniml 7352d 17h /t48/tags/rel_0_1_beta/sw/
70 clean test cell before make arniml 7358d 09h /t48/tags/rel_0_1_beta/sw/
69 fix name of istrobe arniml 7358d 09h /t48/tags/rel_0_1_beta/sw/
61 expand script for dump compare arniml 7360d 06h /t48/tags/rel_0_1_beta/sw/
58 add periodic interrupt arniml 7361d 06h /t48/tags/rel_0_1_beta/sw/
57 abort if no interrupt occurs arniml 7361d 06h /t48/tags/rel_0_1_beta/sw/
52 + fix bug in PSW[3]
+ read SP properly for dump
arniml 7362d 07h /t48/tags/rel_0_1_beta/sw/
51 + implement Port1 and Port2
+ connect T0 and T1
+ return proper program memory contents
arniml 7362d 07h /t48/tags/rel_0_1_beta/sw/
49 Imported sources arniml 7367d 09h /t48/tags/rel_0_1_beta/sw/
48 update copyright notice arniml 7367d 09h /t48/tags/rel_0_1_beta/sw/
47 initial check-in arniml 7367d 09h /t48/tags/rel_0_1_beta/sw/
46 fix test arniml 7369d 06h /t48/tags/rel_0_1_beta/sw/
42 change test values that match better to the test case arniml 7370d 10h /t48/tags/rel_0_1_beta/sw/
41 expand PATH arniml 7370d 10h /t48/tags/rel_0_1_beta/sw/
39 initial check-in arniml 7372d 14h /t48/tags/rel_0_1_beta/sw/

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