URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_1_beta/] [sw/] - Rev 58

Rev	Log message	Author	Age	Path
58	add periodic interrupt	arniml	7397d 01h	/t48/tags/rel_0_1_beta/sw/
57	abort if no interrupt occurs	arniml	7397d 01h	/t48/tags/rel_0_1_beta/sw/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7398d 02h	/t48/tags/rel_0_1_beta/sw/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7398d 02h	/t48/tags/rel_0_1_beta/sw/
49	Imported sources	arniml	7403d 04h	/t48/tags/rel_0_1_beta/sw/
48	update copyright notice	arniml	7403d 04h	/t48/tags/rel_0_1_beta/sw/
47	initial check-in	arniml	7403d 04h	/t48/tags/rel_0_1_beta/sw/
46	fix test	arniml	7405d 01h	/t48/tags/rel_0_1_beta/sw/
42	change test values that match better to the test case	arniml	7406d 05h	/t48/tags/rel_0_1_beta/sw/
41	expand PATH	arniml	7406d 05h	/t48/tags/rel_0_1_beta/sw/
39	initial check-in	arniml	7408d 09h	/t48/tags/rel_0_1_beta/sw/
36	make calculation of expected value more readable	arniml	7408d 10h	/t48/tags/rel_0_1_beta/sw/
35	initial check-in	arniml	7411d 02h	/t48/tags/rel_0_1_beta/sw/
34	fix test wrt AC	arniml	7414d 03h	/t48/tags/rel_0_1_beta/sw/
25	initial check-in	arniml	7415d 02h	/t48/tags/rel_0_1_beta/sw/
18	fix constant format	arniml	7417d 00h	/t48/tags/rel_0_1_beta/sw/
17	fix test	arniml	7417d 00h	/t48/tags/rel_0_1_beta/sw/
15	initial check-in	arniml	7418d 00h	/t48/tags/rel_0_1_beta/sw/
14	initial check-in	arniml	7418d 00h	/t48/tags/rel_0_1_beta/sw/
12	Imported sources	arniml	7418d 01h	/t48/tags/rel_0_1_beta/sw/