URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_1_beta/] [sw/] [i8039emu/] - Rev 292

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5607d 18h	/t48/tags/rel_0_1_beta/sw/i8039emu/
251	This commit was manufactured by cvs2svn to create tag 'rel_0_1_beta'.		6578d 03h	/t48/tags/rel_0_1_beta/sw/i8039emu/
88	allow memory bank switching during interrupts	arniml	7381d 10h	/t48/tags/rel_0_1_beta/sw/i8039emu/
74	enhance pass/fail detection	arniml	7388d 16h	/t48/tags/rel_0_1_beta/sw/i8039emu/
58	add periodic interrupt	arniml	7397d 06h	/t48/tags/rel_0_1_beta/sw/i8039emu/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7398d 07h	/t48/tags/rel_0_1_beta/sw/i8039emu/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7398d 07h	/t48/tags/rel_0_1_beta/sw/i8039emu/
49	Imported sources	arniml	7403d 08h	/t48/tags/rel_0_1_beta/sw/i8039emu/