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[/] [t48/] [tags/] [rel_0_2_beta/] [rtl/] [vhdl/] - Rev 329

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Rev Log message Author Age Path
292 New directory structure. root 5589d 21h /t48/tags/rel_0_2_beta/rtl/vhdl/
252 This commit was manufactured by cvs2svn to create tag 'rel_0_2_beta'. 6560d 06h /t48/tags/rel_0_2_beta/rtl/vhdl/
108 Fix for:
External Program Memory ignored when EA = 0
arniml 7344d 09h /t48/tags/rel_0_2_beta/rtl/vhdl/
107 tie EA to '1' arniml 7344d 09h /t48/tags/rel_0_2_beta/rtl/vhdl/
106 clean-up use of ea_i arniml 7344d 09h /t48/tags/rel_0_2_beta/rtl/vhdl/
101 assert p2_read_p2_o when expander port is read arniml 7347d 16h /t48/tags/rel_0_2_beta/rtl/vhdl/
100 reorder data_o generation arniml 7347d 16h /t48/tags/rel_0_2_beta/rtl/vhdl/
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7347d 17h /t48/tags/rel_0_2_beta/rtl/vhdl/
92 work around bug in Quartus II 4.0 arniml 7348d 15h /t48/tags/rel_0_2_beta/rtl/vhdl/
91 fix edge detector bug for counter arniml 7348d 15h /t48/tags/rel_0_2_beta/rtl/vhdl/
86 update notice about expander port instructions arniml 7363d 19h /t48/tags/rel_0_2_beta/rtl/vhdl/
78 adjust external timing of BUS arniml 7369d 14h /t48/tags/rel_0_2_beta/rtl/vhdl/
77 move from std_logic_arith to numeric_std arniml 7370d 07h /t48/tags/rel_0_2_beta/rtl/vhdl/
73 removed dummy_s - workaround not longer needed for GHDL 0.11.1 arniml 7370d 19h /t48/tags/rel_0_2_beta/rtl/vhdl/
72 removed superfluous signal from sensitivity list arniml 7370d 19h /t48/tags/rel_0_2_beta/rtl/vhdl/
66 add temporary workaround for GHDL 0.11 arniml 7376d 12h /t48/tags/rel_0_2_beta/rtl/vhdl/
65 clean up sensitivity list arniml 7376d 12h /t48/tags/rel_0_2_beta/rtl/vhdl/
64 + enhance instruction strobe generation
+ rework address output under EA=1 conditions
arniml 7376d 12h /t48/tags/rel_0_2_beta/rtl/vhdl/
63 reset machine state to MSTATE3 to allow proper instruction fetch
after reset
arniml 7376d 12h /t48/tags/rel_0_2_beta/rtl/vhdl/
62 initial check-in arniml 7376d 12h /t48/tags/rel_0_2_beta/rtl/vhdl/

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