URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_2_beta/] [sw/] - Rev 90

Rev	Log message	Author	Age	Path
90	intial check-in	arniml	7359d 14h	/t48/tags/rel_0_2_beta/sw/
89	initial check-in	arniml	7373d 10h	/t48/tags/rel_0_2_beta/sw/
88	allow memory bank switching during interrupts	arniml	7374d 12h	/t48/tags/rel_0_2_beta/sw/
87	abort gracfullt if memory bank switching does not work	arniml	7374d 12h	/t48/tags/rel_0_2_beta/sw/
85	initial check-in	arniml	7374d 18h	/t48/tags/rel_0_2_beta/sw/
74	enhance pass/fail detection	arniml	7381d 18h	/t48/tags/rel_0_2_beta/sw/
70	clean test cell before make	arniml	7387d 11h	/t48/tags/rel_0_2_beta/sw/
69	fix name of istrobe	arniml	7387d 11h	/t48/tags/rel_0_2_beta/sw/
61	expand script for dump compare	arniml	7389d 07h	/t48/tags/rel_0_2_beta/sw/
58	add periodic interrupt	arniml	7390d 07h	/t48/tags/rel_0_2_beta/sw/
57	abort if no interrupt occurs	arniml	7390d 08h	/t48/tags/rel_0_2_beta/sw/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7391d 09h	/t48/tags/rel_0_2_beta/sw/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7391d 09h	/t48/tags/rel_0_2_beta/sw/
49	Imported sources	arniml	7396d 10h	/t48/tags/rel_0_2_beta/sw/
48	update copyright notice	arniml	7396d 10h	/t48/tags/rel_0_2_beta/sw/
47	initial check-in	arniml	7396d 10h	/t48/tags/rel_0_2_beta/sw/
46	fix test	arniml	7398d 07h	/t48/tags/rel_0_2_beta/sw/
42	change test values that match better to the test case	arniml	7399d 11h	/t48/tags/rel_0_2_beta/sw/
41	expand PATH	arniml	7399d 11h	/t48/tags/rel_0_2_beta/sw/
39	initial check-in	arniml	7401d 15h	/t48/tags/rel_0_2_beta/sw/