URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] - Rev 121

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
121	update bug description for Program Memory bank can be switched during interrupt	arniml	7312d 22h	/t48/tags/rel_0_3_beta/
120	Fix bug report: "Program Memory bank can be switched during interrupt" int module emits int_in_progress signal that is used inside the decoder to hold mb low for JMP and CALL during interrupts	arniml	7312d 22h	/t48/tags/rel_0_3_beta/
119	add int_in_progress_o to entity of int module	arniml	7312d 22h	/t48/tags/rel_0_3_beta/
118	test MB/interrupt behaviour according to bug report "Program Memory bank can be switched during interrupt"	arniml	7312d 22h	/t48/tags/rel_0_3_beta/
117	add bug Program Memory bank can be switched during interrupt	arniml	7313d 22h	/t48/tags/rel_0_3_beta/
116	adapt to GHDL 0.12 / gcc 3.4.0	arniml	7341d 22h	/t48/tags/rel_0_3_beta/
115	extend description	arniml	7343d 02h	/t48/tags/rel_0_3_beta/
114	initial check-in	arniml	7346d 22h	/t48/tags/rel_0_3_beta/
113	generate two ROM files based on address: + 0 - 2047 : 2k internal ROM + 2048 - 4095 : 2k external ROM	arniml	7353d 08h	/t48/tags/rel_0_3_beta/
112	update tb_behav_c0 for new ROM layout	arniml	7353d 08h	/t48/tags/rel_0_3_beta/
111	split 4k internal ROM into + 2k internal ROM + 2k external ROM EA of t48_core is driven by MSB of internal ROM address if upper 2k block is selected, the system switches to EA mode on the fly	arniml	7353d 08h	/t48/tags/rel_0_3_beta/
110	exchange syn_rom for lpm_rom	arniml	7353d 08h	/t48/tags/rel_0_3_beta/
109	add new bug for release 0.1 BETA	arniml	7353d 21h	/t48/tags/rel_0_3_beta/
108	Fix for: External Program Memory ignored when EA = 0	arniml	7353d 21h	/t48/tags/rel_0_3_beta/
107	tie EA to '1'	arniml	7353d 21h	/t48/tags/rel_0_3_beta/
106	clean-up use of ea_i	arniml	7353d 21h	/t48/tags/rel_0_3_beta/
105	initial check-in describe bugs of release 0.1 BETA	arniml	7356d 07h	/t48/tags/rel_0_3_beta/
104	add white_box directory to test suite	arniml	7357d 04h	/t48/tags/rel_0_3_beta/
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7357d 04h	/t48/tags/rel_0_3_beta/
102	update for changes in address space of external memory	arniml	7357d 04h	/t48/tags/rel_0_3_beta/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] - Rev 121

Filtering Options