URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [bench/] [vhdl/] - Rev 103

Rev	Log message	Author	Age	Path
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7394d 15h	/t48/tags/rel_0_3_beta/bench/vhdl/
83	connect if_timing to P2 output of T48	arniml	7416d 09h	/t48/tags/rel_0_3_beta/bench/vhdl/
82	check expander timings	arniml	7416d 09h	/t48/tags/rel_0_3_beta/bench/vhdl/
81	initial check-in	arniml	7416d 13h	/t48/tags/rel_0_3_beta/bench/vhdl/
80	added if_timing	arniml	7416d 13h	/t48/tags/rel_0_3_beta/bench/vhdl/
68	connect T0 and T1 to P1	arniml	7423d 10h	/t48/tags/rel_0_3_beta/bench/vhdl/
67	initial check-in	arniml	7423d 10h	/t48/tags/rel_0_3_beta/bench/vhdl/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7427d 09h	/t48/tags/rel_0_3_beta/bench/vhdl/
33	rename pX_limp to pX_low_imp	arniml	7443d 10h	/t48/tags/rel_0_3_beta/bench/vhdl/
30	connect prog_n_o	arniml	7444d 08h	/t48/tags/rel_0_3_beta/bench/vhdl/
19	enhance simulation result string	arniml	7446d 07h	/t48/tags/rel_0_3_beta/bench/vhdl/
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7448d 06h	/t48/tags/rel_0_3_beta/bench/vhdl/
8	initial check-in	arniml	7448d 08h	/t48/tags/rel_0_3_beta/bench/vhdl/