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[/] [t48/] [tags/] [rel_0_3_beta/] [bench/] [vhdl/] - Rev 329

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292 New directory structure. root 5588d 23h /t48/tags/rel_0_3_beta/bench/vhdl/
253 This commit was manufactured by cvs2svn to create tag 'rel_0_3_beta'. 6559d 08h /t48/tags/rel_0_3_beta/bench/vhdl/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7342d 22h /t48/tags/rel_0_3_beta/bench/vhdl/
110 exchange syn_rom for lpm_rom arniml 7342d 22h /t48/tags/rel_0_3_beta/bench/vhdl/
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7346d 18h /t48/tags/rel_0_3_beta/bench/vhdl/
83 connect if_timing to P2 output of T48 arniml 7368d 12h /t48/tags/rel_0_3_beta/bench/vhdl/
82 check expander timings arniml 7368d 12h /t48/tags/rel_0_3_beta/bench/vhdl/
81 initial check-in arniml 7368d 17h /t48/tags/rel_0_3_beta/bench/vhdl/
80 added if_timing arniml 7368d 17h /t48/tags/rel_0_3_beta/bench/vhdl/
68 connect T0 and T1 to P1 arniml 7375d 14h /t48/tags/rel_0_3_beta/bench/vhdl/
67 initial check-in arniml 7375d 14h /t48/tags/rel_0_3_beta/bench/vhdl/
56 wait for instruction strobe after final end-of-simulation detection
this ensures that the last mov instruction is part of the dump and
enables 100% matching with i8039 simulator		 arniml 7379d 12h /t48/tags/rel_0_3_beta/bench/vhdl/
33 rename pX_limp to pX_low_imp arniml 7395d 13h /t48/tags/rel_0_3_beta/bench/vhdl/
30 connect prog_n_o arniml 7396d 12h /t48/tags/rel_0_3_beta/bench/vhdl/
19 enhance simulation result string arniml 7398d 10h /t48/tags/rel_0_3_beta/bench/vhdl/
10 put ext_ram on falling clock edge to sample the write enable proberly arniml 7400d 10h /t48/tags/rel_0_3_beta/bench/vhdl/
8 initial check-in arniml 7400d 11h /t48/tags/rel_0_3_beta/bench/vhdl/

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