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[/] [t48/] [tags/] [rel_0_3_beta/] [bench/] [vhdl/] - Rev 33

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Rev Log message Author Age Path
33 rename pX_limp to pX_low_imp arniml 7413d 22h /t48/tags/rel_0_3_beta/bench/vhdl/
30 connect prog_n_o arniml 7414d 20h /t48/tags/rel_0_3_beta/bench/vhdl/
19 enhance simulation result string arniml 7416d 19h /t48/tags/rel_0_3_beta/bench/vhdl/
10 put ext_ram on falling clock edge to sample the write enable proberly arniml 7418d 18h /t48/tags/rel_0_3_beta/bench/vhdl/
8 initial check-in arniml 7418d 20h /t48/tags/rel_0_3_beta/bench/vhdl/

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