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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [rtl/] - Rev 59

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Rev	Log message	Author	Age	Path
59	increment prescaler with MSTATE4	arniml	7426d 07h	/t48/tags/rel_0_3_beta/rtl/
54	- add tb_istrobe_s	arniml	7427d 09h	/t48/tags/rel_0_3_beta/rtl/
53	make istrobe visible through testbench package	arniml	7427d 09h	/t48/tags/rel_0_3_beta/rtl/
45	remove unused signals	arniml	7434d 07h	/t48/tags/rel_0_3_beta/rtl/
44	default assignment for aux_carry_o	arniml	7434d 08h	/t48/tags/rel_0_3_beta/rtl/
43	fix sensitivity list	arniml	7435d 09h	/t48/tags/rel_0_3_beta/rtl/
40	rework adder and force resource sharing between ADD, INC and DEC	arniml	7435d 11h	/t48/tags/rel_0_3_beta/rtl/
38	add measures to implement XCHD	arniml	7437d 15h	/t48/tags/rel_0_3_beta/rtl/
37	add dump_compare support	arniml	7437d 15h	/t48/tags/rel_0_3_beta/rtl/
32	rename pX_limp to pX_low_imp	arniml	7443d 10h	/t48/tags/rel_0_3_beta/rtl/
29	take auxiliary carry from direct ALU connection	arniml	7444d 08h	/t48/tags/rel_0_3_beta/rtl/
28	update wiring for DA support	arniml	7444d 08h	/t48/tags/rel_0_3_beta/rtl/
27	implemented mnemonic DA	arniml	7444d 08h	/t48/tags/rel_0_3_beta/rtl/
26	support for DA instruction	arniml	7444d 08h	/t48/tags/rel_0_3_beta/rtl/
24	connect control signal for Port 2 expander	arniml	7444d 16h	/t48/tags/rel_0_3_beta/rtl/
23	rework Port 2 expander handling	arniml	7444d 16h	/t48/tags/rel_0_3_beta/rtl/
22	merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A	arniml	7444d 16h	/t48/tags/rel_0_3_beta/rtl/
21	implement mnemonics: + MOVD_A_PP + OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A	arniml	7444d 16h	/t48/tags/rel_0_3_beta/rtl/
20	move code for PROG out of if-branch for xtal3_s	arniml	7444d 16h	/t48/tags/rel_0_3_beta/rtl/
7	initial check-in	arniml	7448d 08h	/t48/tags/rel_0_3_beta/rtl/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [rtl/] - Rev 59

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