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[/] [t48/] [tags/] [rel_0_3_beta/] [rtl/] [vhdl/] - Rev 65

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Rev Log message Author Age Path
65 clean up sensitivity list arniml 7394d 03h /t48/tags/rel_0_3_beta/rtl/vhdl/
64 + enhance instruction strobe generation
+ rework address output under EA=1 conditions
arniml 7394d 03h /t48/tags/rel_0_3_beta/rtl/vhdl/
63 reset machine state to MSTATE3 to allow proper instruction fetch
after reset
arniml 7394d 03h /t48/tags/rel_0_3_beta/rtl/vhdl/
62 initial check-in arniml 7394d 03h /t48/tags/rel_0_3_beta/rtl/vhdl/
60 + add marker for injected calls
+ suppress intstruction strobes for injected calls
arniml 7397d 00h /t48/tags/rel_0_3_beta/rtl/vhdl/
59 increment prescaler with MSTATE4 arniml 7397d 00h /t48/tags/rel_0_3_beta/rtl/vhdl/
54 - add tb_istrobe_s arniml 7398d 01h /t48/tags/rel_0_3_beta/rtl/vhdl/
53 make istrobe visible through testbench package arniml 7398d 01h /t48/tags/rel_0_3_beta/rtl/vhdl/
45 remove unused signals arniml 7405d 00h /t48/tags/rel_0_3_beta/rtl/vhdl/
44 default assignment for aux_carry_o arniml 7405d 01h /t48/tags/rel_0_3_beta/rtl/vhdl/
43 fix sensitivity list arniml 7406d 02h /t48/tags/rel_0_3_beta/rtl/vhdl/
40 rework adder and force resource sharing between ADD, INC and DEC arniml 7406d 04h /t48/tags/rel_0_3_beta/rtl/vhdl/
38 add measures to implement XCHD arniml 7408d 08h /t48/tags/rel_0_3_beta/rtl/vhdl/
37 add dump_compare support arniml 7408d 08h /t48/tags/rel_0_3_beta/rtl/vhdl/
32 rename pX_limp to pX_low_imp arniml 7414d 03h /t48/tags/rel_0_3_beta/rtl/vhdl/
29 take auxiliary carry from direct ALU connection arniml 7415d 01h /t48/tags/rel_0_3_beta/rtl/vhdl/
28 update wiring for DA support arniml 7415d 01h /t48/tags/rel_0_3_beta/rtl/vhdl/
27 implemented mnemonic DA arniml 7415d 01h /t48/tags/rel_0_3_beta/rtl/vhdl/
26 support for DA instruction arniml 7415d 01h /t48/tags/rel_0_3_beta/rtl/vhdl/
24 connect control signal for Port 2 expander arniml 7415d 09h /t48/tags/rel_0_3_beta/rtl/vhdl/

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