URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [sw/] - Rev 89

Rev	Log message	Author	Age	Path
89	initial check-in	arniml	7371d 23h	/t48/tags/rel_0_3_beta/sw/
88	allow memory bank switching during interrupts	arniml	7373d 01h	/t48/tags/rel_0_3_beta/sw/
87	abort gracfullt if memory bank switching does not work	arniml	7373d 01h	/t48/tags/rel_0_3_beta/sw/
85	initial check-in	arniml	7373d 06h	/t48/tags/rel_0_3_beta/sw/
74	enhance pass/fail detection	arniml	7380d 06h	/t48/tags/rel_0_3_beta/sw/
70	clean test cell before make	arniml	7385d 23h	/t48/tags/rel_0_3_beta/sw/
69	fix name of istrobe	arniml	7385d 23h	/t48/tags/rel_0_3_beta/sw/
61	expand script for dump compare	arniml	7387d 20h	/t48/tags/rel_0_3_beta/sw/
58	add periodic interrupt	arniml	7388d 20h	/t48/tags/rel_0_3_beta/sw/
57	abort if no interrupt occurs	arniml	7388d 20h	/t48/tags/rel_0_3_beta/sw/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7389d 21h	/t48/tags/rel_0_3_beta/sw/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7389d 21h	/t48/tags/rel_0_3_beta/sw/
49	Imported sources	arniml	7394d 23h	/t48/tags/rel_0_3_beta/sw/
48	update copyright notice	arniml	7394d 23h	/t48/tags/rel_0_3_beta/sw/
47	initial check-in	arniml	7394d 23h	/t48/tags/rel_0_3_beta/sw/
46	fix test	arniml	7396d 20h	/t48/tags/rel_0_3_beta/sw/
42	change test values that match better to the test case	arniml	7398d 00h	/t48/tags/rel_0_3_beta/sw/
41	expand PATH	arniml	7398d 00h	/t48/tags/rel_0_3_beta/sw/
39	initial check-in	arniml	7400d 04h	/t48/tags/rel_0_3_beta/sw/
36	make calculation of expected value more readable	arniml	7400d 04h	/t48/tags/rel_0_3_beta/sw/