URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [sw/] - Rev 97

Rev	Log message	Author	Age	Path
97	initial check-in	arniml	7348d 20h	/t48/tags/rel_0_3_beta/sw/
96	select dedicated directorie(s) for regression	arniml	7349d 17h	/t48/tags/rel_0_3_beta/sw/
95	check counter inactivity	arniml	7349d 17h	/t48/tags/rel_0_3_beta/sw/
94	initial check-in	arniml	7349d 17h	/t48/tags/rel_0_3_beta/sw/
90	intial check-in	arniml	7349d 18h	/t48/tags/rel_0_3_beta/sw/
89	initial check-in	arniml	7363d 14h	/t48/tags/rel_0_3_beta/sw/
88	allow memory bank switching during interrupts	arniml	7364d 16h	/t48/tags/rel_0_3_beta/sw/
87	abort gracfullt if memory bank switching does not work	arniml	7364d 16h	/t48/tags/rel_0_3_beta/sw/
85	initial check-in	arniml	7364d 22h	/t48/tags/rel_0_3_beta/sw/
74	enhance pass/fail detection	arniml	7371d 22h	/t48/tags/rel_0_3_beta/sw/
70	clean test cell before make	arniml	7377d 15h	/t48/tags/rel_0_3_beta/sw/
69	fix name of istrobe	arniml	7377d 15h	/t48/tags/rel_0_3_beta/sw/
61	expand script for dump compare	arniml	7379d 11h	/t48/tags/rel_0_3_beta/sw/
58	add periodic interrupt	arniml	7380d 12h	/t48/tags/rel_0_3_beta/sw/
57	abort if no interrupt occurs	arniml	7380d 12h	/t48/tags/rel_0_3_beta/sw/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7381d 13h	/t48/tags/rel_0_3_beta/sw/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7381d 13h	/t48/tags/rel_0_3_beta/sw/
49	Imported sources	arniml	7386d 14h	/t48/tags/rel_0_3_beta/sw/
48	update copyright notice	arniml	7386d 14h	/t48/tags/rel_0_3_beta/sw/
47	initial check-in	arniml	7386d 14h	/t48/tags/rel_0_3_beta/sw/