OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_4_beta/] - Rev 117

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
117 add bug
Program Memory bank can be switched during interrupt
arniml 7322d 06h /t48/tags/rel_0_4_beta/
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7350d 06h /t48/tags/rel_0_4_beta/
115 extend description arniml 7351d 10h /t48/tags/rel_0_4_beta/
114 initial check-in arniml 7355d 06h /t48/tags/rel_0_4_beta/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM
arniml 7361d 15h /t48/tags/rel_0_4_beta/
112 update tb_behav_c0 for new ROM layout arniml 7361d 15h /t48/tags/rel_0_4_beta/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly
arniml 7361d 15h /t48/tags/rel_0_4_beta/
110 exchange syn_rom for lpm_rom arniml 7361d 15h /t48/tags/rel_0_4_beta/
109 add new bug for release 0.1 BETA arniml 7362d 04h /t48/tags/rel_0_4_beta/
108 Fix for:
External Program Memory ignored when EA = 0
arniml 7362d 05h /t48/tags/rel_0_4_beta/
107 tie EA to '1' arniml 7362d 05h /t48/tags/rel_0_4_beta/
106 clean-up use of ea_i arniml 7362d 05h /t48/tags/rel_0_4_beta/
105 initial check-in
describe bugs of release 0.1 BETA
arniml 7364d 14h /t48/tags/rel_0_4_beta/
104 add white_box directory to test suite arniml 7365d 12h /t48/tags/rel_0_4_beta/
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data
arniml 7365d 12h /t48/tags/rel_0_4_beta/
102 update for changes in address space of external memory arniml 7365d 12h /t48/tags/rel_0_4_beta/
101 assert p2_read_p2_o when expander port is read arniml 7365d 12h /t48/tags/rel_0_4_beta/
100 reorder data_o generation arniml 7365d 12h /t48/tags/rel_0_4_beta/
99 initial check-in arniml 7365d 12h /t48/tags/rel_0_4_beta/
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7365d 13h /t48/tags/rel_0_4_beta/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.