URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_4_beta/] [bench/] [vhdl/] - Rev 56

Rev	Log message	Author	Age	Path
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7387d 04h	/t48/tags/rel_0_4_beta/bench/vhdl/
33	rename pX_limp to pX_low_imp	arniml	7403d 05h	/t48/tags/rel_0_4_beta/bench/vhdl/
30	connect prog_n_o	arniml	7404d 04h	/t48/tags/rel_0_4_beta/bench/vhdl/
19	enhance simulation result string	arniml	7406d 02h	/t48/tags/rel_0_4_beta/bench/vhdl/
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7408d 02h	/t48/tags/rel_0_4_beta/bench/vhdl/
8	initial check-in	arniml	7408d 03h	/t48/tags/rel_0_4_beta/bench/vhdl/