OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_4_beta/] [rtl/] - Rev 292

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
292 New directory structure. root 5620d 09h /t48/tags/rel_0_4_beta/rtl/
254 This commit was manufactured by cvs2svn to create tag 'rel_0_4_beta'. 6590d 18h /t48/tags/rel_0_4_beta/rtl/
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.
arniml 7260d 19h /t48/tags/rel_0_4_beta/rtl/
129 cleanup copyright notice arniml 7323d 02h /t48/tags/rel_0_4_beta/rtl/
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered
arniml 7330d 06h /t48/tags/rel_0_4_beta/rtl/
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts
arniml 7333d 22h /t48/tags/rel_0_4_beta/rtl/
119 add int_in_progress_o to entity of int module arniml 7333d 22h /t48/tags/rel_0_4_beta/rtl/
108 Fix for:
External Program Memory ignored when EA = 0
arniml 7374d 21h /t48/tags/rel_0_4_beta/rtl/
107 tie EA to '1' arniml 7374d 21h /t48/tags/rel_0_4_beta/rtl/
106 clean-up use of ea_i arniml 7374d 21h /t48/tags/rel_0_4_beta/rtl/
101 assert p2_read_p2_o when expander port is read arniml 7378d 05h /t48/tags/rel_0_4_beta/rtl/
100 reorder data_o generation arniml 7378d 05h /t48/tags/rel_0_4_beta/rtl/
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7378d 05h /t48/tags/rel_0_4_beta/rtl/
92 work around bug in Quartus II 4.0 arniml 7379d 04h /t48/tags/rel_0_4_beta/rtl/
91 fix edge detector bug for counter arniml 7379d 04h /t48/tags/rel_0_4_beta/rtl/
86 update notice about expander port instructions arniml 7394d 07h /t48/tags/rel_0_4_beta/rtl/
78 adjust external timing of BUS arniml 7400d 03h /t48/tags/rel_0_4_beta/rtl/
77 move from std_logic_arith to numeric_std arniml 7400d 20h /t48/tags/rel_0_4_beta/rtl/
73 removed dummy_s - workaround not longer needed for GHDL 0.11.1 arniml 7401d 08h /t48/tags/rel_0_4_beta/rtl/
72 removed superfluous signal from sensitivity list arniml 7401d 08h /t48/tags/rel_0_4_beta/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.