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[/] [t48/] [tags/] [rel_0_4_beta/] [rtl/] [vhdl/] - Rev 303

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5630d 01h	/t48/tags/rel_0_4_beta/rtl/vhdl/
254	This commit was manufactured by cvs2svn to create tag 'rel_0_4_beta'.		6600d 10h	/t48/tags/rel_0_4_beta/rtl/vhdl/
134	Fix bug report: "PSENn Timing" PSEN is now only asserted for the second cycle if explicitely requested by assert_psen_s. The previous implementation asserted PSEN together with RD or WR.	arniml	7270d 11h	/t48/tags/rel_0_4_beta/rtl/vhdl/
129	cleanup copyright notice	arniml	7332d 18h	/t48/tags/rel_0_4_beta/rtl/vhdl/
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7339d 22h	/t48/tags/rel_0_4_beta/rtl/vhdl/
120	Fix bug report: "Program Memory bank can be switched during interrupt" int module emits int_in_progress signal that is used inside the decoder to hold mb low for JMP and CALL during interrupts	arniml	7343d 14h	/t48/tags/rel_0_4_beta/rtl/vhdl/
119	add int_in_progress_o to entity of int module	arniml	7343d 14h	/t48/tags/rel_0_4_beta/rtl/vhdl/
108	Fix for: External Program Memory ignored when EA = 0	arniml	7384d 13h	/t48/tags/rel_0_4_beta/rtl/vhdl/
107	tie EA to '1'	arniml	7384d 13h	/t48/tags/rel_0_4_beta/rtl/vhdl/
106	clean-up use of ea_i	arniml	7384d 13h	/t48/tags/rel_0_4_beta/rtl/vhdl/
101	assert p2_read_p2_o when expander port is read	arniml	7387d 21h	/t48/tags/rel_0_4_beta/rtl/vhdl/
100	reorder data_o generation	arniml	7387d 21h	/t48/tags/rel_0_4_beta/rtl/vhdl/
98	Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"	arniml	7387d 21h	/t48/tags/rel_0_4_beta/rtl/vhdl/
92	work around bug in Quartus II 4.0	arniml	7388d 20h	/t48/tags/rel_0_4_beta/rtl/vhdl/
91	fix edge detector bug for counter	arniml	7388d 20h	/t48/tags/rel_0_4_beta/rtl/vhdl/
86	update notice about expander port instructions	arniml	7403d 23h	/t48/tags/rel_0_4_beta/rtl/vhdl/
78	adjust external timing of BUS	arniml	7409d 19h	/t48/tags/rel_0_4_beta/rtl/vhdl/
77	move from std_logic_arith to numeric_std	arniml	7410d 11h	/t48/tags/rel_0_4_beta/rtl/vhdl/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7411d 00h	/t48/tags/rel_0_4_beta/rtl/vhdl/
72	removed superfluous signal from sensitivity list	arniml	7411d 00h	/t48/tags/rel_0_4_beta/rtl/vhdl/

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[/] [t48/] [tags/] [rel_0_4_beta/] [rtl/] [vhdl/] - Rev 303

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