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[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 103

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Rev	Log message	Author	Age	Path
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7348d 23h	/t48/tags/rel_0_5_beta/
102	update for changes in address space of external memory	arniml	7348d 23h	/t48/tags/rel_0_5_beta/
101	assert p2_read_p2_o when expander port is read	arniml	7348d 23h	/t48/tags/rel_0_5_beta/
100	reorder data_o generation	arniml	7348d 23h	/t48/tags/rel_0_5_beta/
99	initial check-in	arniml	7348d 23h	/t48/tags/rel_0_5_beta/
98	Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"	arniml	7349d 00h	/t48/tags/rel_0_5_beta/
97	initial check-in	arniml	7349d 00h	/t48/tags/rel_0_5_beta/
96	select dedicated directorie(s) for regression	arniml	7349d 22h	/t48/tags/rel_0_5_beta/
95	check counter inactivity	arniml	7349d 22h	/t48/tags/rel_0_5_beta/
94	initial check-in	arniml	7349d 22h	/t48/tags/rel_0_5_beta/
93	add support for line coverage evaluation with gcov	arniml	7349d 22h	/t48/tags/rel_0_5_beta/
92	work around bug in Quartus II 4.0	arniml	7349d 22h	/t48/tags/rel_0_5_beta/
91	fix edge detector bug for counter	arniml	7349d 22h	/t48/tags/rel_0_5_beta/
90	intial check-in	arniml	7349d 22h	/t48/tags/rel_0_5_beta/
89	initial check-in	arniml	7363d 19h	/t48/tags/rel_0_5_beta/
88	allow memory bank switching during interrupts	arniml	7364d 21h	/t48/tags/rel_0_5_beta/
87	abort gracfullt if memory bank switching does not work	arniml	7364d 21h	/t48/tags/rel_0_5_beta/
86	update notice about expander port instructions	arniml	7365d 02h	/t48/tags/rel_0_5_beta/
85	initial check-in	arniml	7365d 02h	/t48/tags/rel_0_5_beta/
84	add if_timing module	arniml	7370d 17h	/t48/tags/rel_0_5_beta/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 103

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