URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 122

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Rev	Log message	Author	Age	Path
122	test MB after return from interrupt	arniml	7301d 00h	/t48/tags/rel_0_5_beta/
121	update bug description for Program Memory bank can be switched during interrupt	arniml	7303d 17h	/t48/tags/rel_0_5_beta/
120	Fix bug report: "Program Memory bank can be switched during interrupt" int module emits int_in_progress signal that is used inside the decoder to hold mb low for JMP and CALL during interrupts	arniml	7303d 17h	/t48/tags/rel_0_5_beta/
119	add int_in_progress_o to entity of int module	arniml	7303d 17h	/t48/tags/rel_0_5_beta/
118	test MB/interrupt behaviour according to bug report "Program Memory bank can be switched during interrupt"	arniml	7303d 17h	/t48/tags/rel_0_5_beta/
117	add bug Program Memory bank can be switched during interrupt	arniml	7304d 17h	/t48/tags/rel_0_5_beta/
116	adapt to GHDL 0.12 / gcc 3.4.0	arniml	7332d 17h	/t48/tags/rel_0_5_beta/
115	extend description	arniml	7333d 22h	/t48/tags/rel_0_5_beta/
114	initial check-in	arniml	7337d 17h	/t48/tags/rel_0_5_beta/
113	generate two ROM files based on address: + 0 - 2047 : 2k internal ROM + 2048 - 4095 : 2k external ROM	arniml	7344d 03h	/t48/tags/rel_0_5_beta/
112	update tb_behav_c0 for new ROM layout	arniml	7344d 03h	/t48/tags/rel_0_5_beta/
111	split 4k internal ROM into + 2k internal ROM + 2k external ROM EA of t48_core is driven by MSB of internal ROM address if upper 2k block is selected, the system switches to EA mode on the fly	arniml	7344d 03h	/t48/tags/rel_0_5_beta/
110	exchange syn_rom for lpm_rom	arniml	7344d 03h	/t48/tags/rel_0_5_beta/
109	add new bug for release 0.1 BETA	arniml	7344d 16h	/t48/tags/rel_0_5_beta/
108	Fix for: External Program Memory ignored when EA = 0	arniml	7344d 16h	/t48/tags/rel_0_5_beta/
107	tie EA to '1'	arniml	7344d 16h	/t48/tags/rel_0_5_beta/
106	clean-up use of ea_i	arniml	7344d 16h	/t48/tags/rel_0_5_beta/
105	initial check-in describe bugs of release 0.1 BETA	arniml	7347d 02h	/t48/tags/rel_0_5_beta/
104	add white_box directory to test suite	arniml	7347d 23h	/t48/tags/rel_0_5_beta/
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7347d 23h	/t48/tags/rel_0_5_beta/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 122

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