URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 146

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
146	add bug RD' and WR' not asserted for INS A, BUS and OUTL BUS, A	arniml	7223d 05h	/t48/tags/rel_0_5_beta/
145	remove PROG and end of XTAL2, see comment for details	arniml	7223d 07h	/t48/tags/rel_0_5_beta/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7223d 07h	/t48/tags/rel_0_5_beta/
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7223d 07h	/t48/tags/rel_0_5_beta/
142	deassert rd_q, wr_q and prog_q at end of XTAL3	arniml	7223d 07h	/t48/tags/rel_0_5_beta/
141	disable external memory to avoid conflicts with outl a, bus	arniml	7223d 07h	/t48/tags/rel_0_5_beta/
140	remove tAW sanity check conflicts with OUTL A, BUS	arniml	7223d 07h	/t48/tags/rel_0_5_beta/
139	add bug P1 constantly in push-pull mode in t8048	arniml	7224d 18h	/t48/tags/rel_0_5_beta/
138	Fix for: P1 constantly in push-pull mode in t8048	arniml	7224d 18h	/t48/tags/rel_0_5_beta/
137	add link to COMPILE_LIST	arniml	7262d 06h	/t48/tags/rel_0_5_beta/
136	initial check-in	arniml	7262d 06h	/t48/tags/rel_0_5_beta/
135	add bug PSENn Timing	arniml	7266d 17h	/t48/tags/rel_0_5_beta/
134	Fix bug report: "PSENn Timing" PSEN is now only asserted for the second cycle if explicitely requested by assert_psen_s. The previous implementation asserted PSEN together with RD or WR.	arniml	7267d 02h	/t48/tags/rel_0_5_beta/
133	add checks for PSEN	arniml	7267d 02h	/t48/tags/rel_0_5_beta/
132	stop simulation upon assertion error	arniml	7267d 03h	/t48/tags/rel_0_5_beta/
131	update	arniml	7267d 03h	/t48/tags/rel_0_5_beta/
130	initial check-in	arniml	7267d 03h	/t48/tags/rel_0_5_beta/
129	cleanup copyright notice	arniml	7329d 10h	/t48/tags/rel_0_5_beta/
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7336d 14h	/t48/tags/rel_0_5_beta/
127	+ log status of A11 properly during interrupt routines + trigger counter on negative edge of T1 instead of positive edge	arniml	7336d 15h	/t48/tags/rel_0_5_beta/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 146

Filtering Options