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[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 147

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147 initial check-in for release 0.5 BETA arniml 7203d 08h /t48/tags/rel_0_5_beta/
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A		 arniml 7204d 08h /t48/tags/rel_0_5_beta/
145 remove PROG and end of XTAL2, see comment for details arniml 7204d 09h /t48/tags/rel_0_5_beta/
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7204d 09h /t48/tags/rel_0_5_beta/
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7204d 10h /t48/tags/rel_0_5_beta/
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7204d 10h /t48/tags/rel_0_5_beta/
141 disable external memory to avoid conflicts with outl a, bus arniml 7204d 10h /t48/tags/rel_0_5_beta/
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7204d 10h /t48/tags/rel_0_5_beta/
139 add bug
P1 constantly in push-pull mode in t8048		 arniml 7205d 20h /t48/tags/rel_0_5_beta/
138 Fix for:
P1 constantly in push-pull mode in t8048		 arniml 7205d 20h /t48/tags/rel_0_5_beta/
137 add link to COMPILE_LIST arniml 7243d 08h /t48/tags/rel_0_5_beta/
136 initial check-in arniml 7243d 08h /t48/tags/rel_0_5_beta/
135 add bug
PSENn Timing		 arniml 7247d 19h /t48/tags/rel_0_5_beta/
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7248d 05h /t48/tags/rel_0_5_beta/
133 add checks for PSEN arniml 7248d 05h /t48/tags/rel_0_5_beta/
132 stop simulation upon assertion error arniml 7248d 05h /t48/tags/rel_0_5_beta/
131 update arniml 7248d 05h /t48/tags/rel_0_5_beta/
130 initial check-in arniml 7248d 05h /t48/tags/rel_0_5_beta/
129 cleanup copyright notice arniml 7310d 12h /t48/tags/rel_0_5_beta/
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7317d 16h /t48/tags/rel_0_5_beta/

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