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[/] [t48/] [tags/] [rel_0_5_beta/] [bench/] - Rev 292

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292 New directory structure. root 5569d 23h /t48/tags/rel_0_5_beta/bench/
255 This commit was manufactured by cvs2svn to create tag 'rel_0_5_beta'. 6540d 08h /t48/tags/rel_0_5_beta/bench/
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7166d 14h /t48/tags/rel_0_5_beta/bench/
133 add checks for PSEN arniml 7210d 09h /t48/tags/rel_0_5_beta/bench/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7323d 22h /t48/tags/rel_0_5_beta/bench/
110 exchange syn_rom for lpm_rom arniml 7323d 22h /t48/tags/rel_0_5_beta/bench/
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7327d 18h /t48/tags/rel_0_5_beta/bench/
83 connect if_timing to P2 output of T48 arniml 7349d 12h /t48/tags/rel_0_5_beta/bench/
82 check expander timings arniml 7349d 13h /t48/tags/rel_0_5_beta/bench/
81 initial check-in arniml 7349d 17h /t48/tags/rel_0_5_beta/bench/
80 added if_timing arniml 7349d 17h /t48/tags/rel_0_5_beta/bench/
68 connect T0 and T1 to P1 arniml 7356d 14h /t48/tags/rel_0_5_beta/bench/
67 initial check-in arniml 7356d 14h /t48/tags/rel_0_5_beta/bench/
56 wait for instruction strobe after final end-of-simulation detection
this ensures that the last mov instruction is part of the dump and
enables 100% matching with i8039 simulator		 arniml 7360d 12h /t48/tags/rel_0_5_beta/bench/
33 rename pX_limp to pX_low_imp arniml 7376d 13h /t48/tags/rel_0_5_beta/bench/
30 connect prog_n_o arniml 7377d 12h /t48/tags/rel_0_5_beta/bench/
19 enhance simulation result string arniml 7379d 11h /t48/tags/rel_0_5_beta/bench/
10 put ext_ram on falling clock edge to sample the write enable proberly arniml 7381d 10h /t48/tags/rel_0_5_beta/bench/
8 initial check-in arniml 7381d 11h /t48/tags/rel_0_5_beta/bench/

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