URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] [bench/] [vhdl/] - Rev 83

Rev	Log message	Author	Age	Path
83	connect if_timing to P2 output of T48	arniml	7418d 00h	/t48/tags/rel_0_5_beta/bench/vhdl/
82	check expander timings	arniml	7418d 00h	/t48/tags/rel_0_5_beta/bench/vhdl/
81	initial check-in	arniml	7418d 04h	/t48/tags/rel_0_5_beta/bench/vhdl/
80	added if_timing	arniml	7418d 04h	/t48/tags/rel_0_5_beta/bench/vhdl/
68	connect T0 and T1 to P1	arniml	7425d 02h	/t48/tags/rel_0_5_beta/bench/vhdl/
67	initial check-in	arniml	7425d 02h	/t48/tags/rel_0_5_beta/bench/vhdl/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7429d 00h	/t48/tags/rel_0_5_beta/bench/vhdl/
33	rename pX_limp to pX_low_imp	arniml	7445d 01h	/t48/tags/rel_0_5_beta/bench/vhdl/
30	connect prog_n_o	arniml	7445d 23h	/t48/tags/rel_0_5_beta/bench/vhdl/
19	enhance simulation result string	arniml	7447d 22h	/t48/tags/rel_0_5_beta/bench/vhdl/
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7449d 21h	/t48/tags/rel_0_5_beta/bench/vhdl/
8	initial check-in	arniml	7449d 23h	/t48/tags/rel_0_5_beta/bench/vhdl/