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[/] [t48/] [tags/] [rel_0_5_beta/] [sw/] - Rev 292

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Rev Log message Author Age Path
292 New directory structure. root 5562d 14h /t48/tags/rel_0_5_beta/sw/
255 This commit was manufactured by cvs2svn to create tag 'rel_0_5_beta'. 6532d 23h /t48/tags/rel_0_5_beta/sw/
141 disable external memory to avoid conflicts with outl a, bus arniml 7159d 05h /t48/tags/rel_0_5_beta/sw/
132 stop simulation upon assertion error arniml 7203d 00h /t48/tags/rel_0_5_beta/sw/
131 update arniml 7203d 00h /t48/tags/rel_0_5_beta/sw/
130 initial check-in arniml 7203d 00h /t48/tags/rel_0_5_beta/sw/
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge
arniml 7272d 12h /t48/tags/rel_0_5_beta/sw/
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell
arniml 7272d 12h /t48/tags/rel_0_5_beta/sw/
125 exclude from dump compare arniml 7272d 12h /t48/tags/rel_0_5_beta/sw/
124 fix wrong handling of MB after return from interrupt arniml 7273d 10h /t48/tags/rel_0_5_beta/sw/
123 support hex file for external ROM arniml 7273d 10h /t48/tags/rel_0_5_beta/sw/
122 test MB after return from interrupt arniml 7273d 10h /t48/tags/rel_0_5_beta/sw/
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"
arniml 7276d 03h /t48/tags/rel_0_5_beta/sw/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM
arniml 7316d 13h /t48/tags/rel_0_5_beta/sw/
104 add white_box directory to test suite arniml 7320d 10h /t48/tags/rel_0_5_beta/sw/
102 update for changes in address space of external memory arniml 7320d 10h /t48/tags/rel_0_5_beta/sw/
99 initial check-in arniml 7320d 10h /t48/tags/rel_0_5_beta/sw/
97 initial check-in arniml 7320d 11h /t48/tags/rel_0_5_beta/sw/
96 select dedicated directorie(s) for regression arniml 7321d 08h /t48/tags/rel_0_5_beta/sw/
95 check counter inactivity arniml 7321d 08h /t48/tags/rel_0_5_beta/sw/

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