URL https://opencores.org/ocsvn/t48/t48/trunk

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[/] [t48/] [tags/] [rel_0_5_beta/] [sw/] - Rev 124

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Rev	Log message	Author	Age	Path
124	fix wrong handling of MB after return from interrupt	arniml	7412d 11h	/t48/tags/rel_0_5_beta/sw/
123	support hex file for external ROM	arniml	7412d 11h	/t48/tags/rel_0_5_beta/sw/
122	test MB after return from interrupt	arniml	7412d 11h	/t48/tags/rel_0_5_beta/sw/
118	test MB/interrupt behaviour according to bug report "Program Memory bank can be switched during interrupt"	arniml	7415d 04h	/t48/tags/rel_0_5_beta/sw/
113	generate two ROM files based on address: + 0 - 2047 : 2k internal ROM + 2048 - 4095 : 2k external ROM	arniml	7455d 14h	/t48/tags/rel_0_5_beta/sw/
104	add white_box directory to test suite	arniml	7459d 11h	/t48/tags/rel_0_5_beta/sw/
102	update for changes in address space of external memory	arniml	7459d 11h	/t48/tags/rel_0_5_beta/sw/
99	initial check-in	arniml	7459d 11h	/t48/tags/rel_0_5_beta/sw/
97	initial check-in	arniml	7459d 12h	/t48/tags/rel_0_5_beta/sw/
96	select dedicated directorie(s) for regression	arniml	7460d 09h	/t48/tags/rel_0_5_beta/sw/
95	check counter inactivity	arniml	7460d 09h	/t48/tags/rel_0_5_beta/sw/
94	initial check-in	arniml	7460d 09h	/t48/tags/rel_0_5_beta/sw/
90	intial check-in	arniml	7460d 10h	/t48/tags/rel_0_5_beta/sw/
89	initial check-in	arniml	7474d 06h	/t48/tags/rel_0_5_beta/sw/
88	allow memory bank switching during interrupts	arniml	7475d 08h	/t48/tags/rel_0_5_beta/sw/
87	abort gracfullt if memory bank switching does not work	arniml	7475d 08h	/t48/tags/rel_0_5_beta/sw/
85	initial check-in	arniml	7475d 14h	/t48/tags/rel_0_5_beta/sw/
74	enhance pass/fail detection	arniml	7482d 14h	/t48/tags/rel_0_5_beta/sw/
70	clean test cell before make	arniml	7488d 06h	/t48/tags/rel_0_5_beta/sw/
69	fix name of istrobe	arniml	7488d 06h	/t48/tags/rel_0_5_beta/sw/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] [sw/] - Rev 124

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