URL https://opencores.org/ocsvn/t48/t48/trunk

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[/] [t48/] [tags/] [rel_0_5_beta/] [sw/] [i8039emu/] - Rev 329

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5589d 19h	/t48/tags/rel_0_5_beta/sw/i8039emu/
255	This commit was manufactured by cvs2svn to create tag 'rel_0_5_beta'.		6560d 03h	/t48/tags/rel_0_5_beta/sw/i8039emu/
127	+ log status of A11 properly during interrupt routines + trigger counter on negative edge of T1 instead of positive edge	arniml	7299d 16h	/t48/tags/rel_0_5_beta/sw/i8039emu/
124	fix wrong handling of MB after return from interrupt	arniml	7300d 14h	/t48/tags/rel_0_5_beta/sw/i8039emu/
123	support hex file for external ROM	arniml	7300d 14h	/t48/tags/rel_0_5_beta/sw/i8039emu/
88	allow memory bank switching during interrupts	arniml	7363d 11h	/t48/tags/rel_0_5_beta/sw/i8039emu/
74	enhance pass/fail detection	arniml	7370d 17h	/t48/tags/rel_0_5_beta/sw/i8039emu/
58	add periodic interrupt	arniml	7379d 06h	/t48/tags/rel_0_5_beta/sw/i8039emu/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7380d 08h	/t48/tags/rel_0_5_beta/sw/i8039emu/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7380d 08h	/t48/tags/rel_0_5_beta/sw/i8039emu/
49	Imported sources	arniml	7385d 09h	/t48/tags/rel_0_5_beta/sw/i8039emu/