URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] [sw/] [verif/] - Rev 329

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5589d 19h	/t48/tags/rel_0_5_beta/sw/verif/
255	This commit was manufactured by cvs2svn to create tag 'rel_0_5_beta'.		6560d 04h	/t48/tags/rel_0_5_beta/sw/verif/
141	disable external memory to avoid conflicts with outl a, bus	arniml	7186d 09h	/t48/tags/rel_0_5_beta/sw/verif/
131	update	arniml	7230d 04h	/t48/tags/rel_0_5_beta/sw/verif/
130	initial check-in	arniml	7230d 04h	/t48/tags/rel_0_5_beta/sw/verif/
125	exclude from dump compare	arniml	7299d 17h	/t48/tags/rel_0_5_beta/sw/verif/
122	test MB after return from interrupt	arniml	7300d 14h	/t48/tags/rel_0_5_beta/sw/verif/
118	test MB/interrupt behaviour according to bug report "Program Memory bank can be switched during interrupt"	arniml	7303d 07h	/t48/tags/rel_0_5_beta/sw/verif/
113	generate two ROM files based on address: + 0 - 2047 : 2k internal ROM + 2048 - 4095 : 2k external ROM	arniml	7343d 17h	/t48/tags/rel_0_5_beta/sw/verif/
102	update for changes in address space of external memory	arniml	7347d 14h	/t48/tags/rel_0_5_beta/sw/verif/
99	initial check-in	arniml	7347d 14h	/t48/tags/rel_0_5_beta/sw/verif/
97	initial check-in	arniml	7347d 15h	/t48/tags/rel_0_5_beta/sw/verif/
95	check counter inactivity	arniml	7348d 12h	/t48/tags/rel_0_5_beta/sw/verif/
94	initial check-in	arniml	7348d 12h	/t48/tags/rel_0_5_beta/sw/verif/
90	intial check-in	arniml	7348d 13h	/t48/tags/rel_0_5_beta/sw/verif/
89	initial check-in	arniml	7362d 09h	/t48/tags/rel_0_5_beta/sw/verif/
87	abort gracfullt if memory bank switching does not work	arniml	7363d 11h	/t48/tags/rel_0_5_beta/sw/verif/
85	initial check-in	arniml	7363d 17h	/t48/tags/rel_0_5_beta/sw/verif/
57	abort if no interrupt occurs	arniml	7379d 07h	/t48/tags/rel_0_5_beta/sw/verif/
46	fix test	arniml	7387d 06h	/t48/tags/rel_0_5_beta/sw/verif/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] [sw/] [verif/] - Rev 329

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