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[/] [t48/] [tags/] [rel_0_6_1_beta/] - Rev 130

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Rev	Log message	Author	Age	Path
130	initial check-in	arniml	7341d 22h	/t48/tags/rel_0_6_1_beta/
129	cleanup copyright notice	arniml	7404d 05h	/t48/tags/rel_0_6_1_beta/
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7411d 09h	/t48/tags/rel_0_6_1_beta/
127	+ log status of A11 properly during interrupt routines + trigger counter on negative edge of T1 instead of positive edge	arniml	7411d 10h	/t48/tags/rel_0_6_1_beta/
126	+ specify hex file for external ROM on i8039 command line + support for no_dump_compare file in test cell	arniml	7411d 10h	/t48/tags/rel_0_6_1_beta/
125	exclude from dump compare	arniml	7411d 10h	/t48/tags/rel_0_6_1_beta/
124	fix wrong handling of MB after return from interrupt	arniml	7412d 07h	/t48/tags/rel_0_6_1_beta/
123	support hex file for external ROM	arniml	7412d 08h	/t48/tags/rel_0_6_1_beta/
122	test MB after return from interrupt	arniml	7412d 08h	/t48/tags/rel_0_6_1_beta/
121	update bug description for Program Memory bank can be switched during interrupt	arniml	7415d 01h	/t48/tags/rel_0_6_1_beta/
120	Fix bug report: "Program Memory bank can be switched during interrupt" int module emits int_in_progress signal that is used inside the decoder to hold mb low for JMP and CALL during interrupts	arniml	7415d 01h	/t48/tags/rel_0_6_1_beta/
119	add int_in_progress_o to entity of int module	arniml	7415d 01h	/t48/tags/rel_0_6_1_beta/
118	test MB/interrupt behaviour according to bug report "Program Memory bank can be switched during interrupt"	arniml	7415d 01h	/t48/tags/rel_0_6_1_beta/
117	add bug Program Memory bank can be switched during interrupt	arniml	7416d 01h	/t48/tags/rel_0_6_1_beta/
116	adapt to GHDL 0.12 / gcc 3.4.0	arniml	7444d 01h	/t48/tags/rel_0_6_1_beta/
115	extend description	arniml	7445d 06h	/t48/tags/rel_0_6_1_beta/
114	initial check-in	arniml	7449d 02h	/t48/tags/rel_0_6_1_beta/
113	generate two ROM files based on address: + 0 - 2047 : 2k internal ROM + 2048 - 4095 : 2k external ROM	arniml	7455d 11h	/t48/tags/rel_0_6_1_beta/
112	update tb_behav_c0 for new ROM layout	arniml	7455d 11h	/t48/tags/rel_0_6_1_beta/
111	split 4k internal ROM into + 2k internal ROM + 2k external ROM EA of t48_core is driven by MSB of internal ROM address if upper 2k block is selected, the system switches to EA mode on the fly	arniml	7455d 11h	/t48/tags/rel_0_6_1_beta/

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[/] [t48/] [tags/] [rel_0_6_1_beta/] - Rev 130

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