Rev |
Log message |
Author |
Age |
Path |
146 |
add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A |
arniml |
7186d 02h |
/t48/tags/rel_0_6_1_beta/ |
145 |
remove PROG and end of XTAL2, see comment for details |
arniml |
7186d 03h |
/t48/tags/rel_0_6_1_beta/ |
144 |
delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR' |
arniml |
7186d 03h |
/t48/tags/rel_0_6_1_beta/ |
143 |
Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle |
arniml |
7186d 04h |
/t48/tags/rel_0_6_1_beta/ |
142 |
deassert rd_q, wr_q and prog_q at end of XTAL3 |
arniml |
7186d 04h |
/t48/tags/rel_0_6_1_beta/ |
141 |
disable external memory to avoid conflicts with outl a, bus |
arniml |
7186d 04h |
/t48/tags/rel_0_6_1_beta/ |
140 |
remove tAW sanity check
conflicts with OUTL A, BUS |
arniml |
7186d 04h |
/t48/tags/rel_0_6_1_beta/ |
139 |
add bug
P1 constantly in push-pull mode in t8048 |
arniml |
7187d 14h |
/t48/tags/rel_0_6_1_beta/ |
138 |
Fix for:
P1 constantly in push-pull mode in t8048 |
arniml |
7187d 14h |
/t48/tags/rel_0_6_1_beta/ |
137 |
add link to COMPILE_LIST |
arniml |
7225d 02h |
/t48/tags/rel_0_6_1_beta/ |
136 |
initial check-in |
arniml |
7225d 02h |
/t48/tags/rel_0_6_1_beta/ |
135 |
add bug
PSENn Timing |
arniml |
7229d 13h |
/t48/tags/rel_0_6_1_beta/ |
134 |
Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR. |
arniml |
7229d 23h |
/t48/tags/rel_0_6_1_beta/ |
133 |
add checks for PSEN |
arniml |
7229d 23h |
/t48/tags/rel_0_6_1_beta/ |
132 |
stop simulation upon assertion error |
arniml |
7229d 23h |
/t48/tags/rel_0_6_1_beta/ |
131 |
update |
arniml |
7229d 23h |
/t48/tags/rel_0_6_1_beta/ |
130 |
initial check-in |
arniml |
7229d 23h |
/t48/tags/rel_0_6_1_beta/ |
129 |
cleanup copyright notice |
arniml |
7292d 06h |
/t48/tags/rel_0_6_1_beta/ |
128 |
counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered |
arniml |
7299d 10h |
/t48/tags/rel_0_6_1_beta/ |
127 |
+ log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge |
arniml |
7299d 11h |
/t48/tags/rel_0_6_1_beta/ |