Rev |
Log message |
Author |
Age |
Path |
152 |
added hierarchy t8048_notri and system components package |
arniml |
7146d 12h |
/t48/tags/rel_0_6_1_beta/ |
151 |
added hierarchy t8048_notri and components package for t48 systems |
arniml |
7146d 12h |
/t48/tags/rel_0_6_1_beta/ |
150 |
intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled |
arniml |
7146d 20h |
/t48/tags/rel_0_6_1_beta/ |
149 |
update |
arniml |
7146d 20h |
/t48/tags/rel_0_6_1_beta/ |
148 |
initial check-in |
arniml |
7146d 20h |
/t48/tags/rel_0_6_1_beta/ |
147 |
initial check-in for release 0.5 BETA |
arniml |
7182d 22h |
/t48/tags/rel_0_6_1_beta/ |
146 |
add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A |
arniml |
7183d 22h |
/t48/tags/rel_0_6_1_beta/ |
145 |
remove PROG and end of XTAL2, see comment for details |
arniml |
7183d 23h |
/t48/tags/rel_0_6_1_beta/ |
144 |
delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR' |
arniml |
7183d 23h |
/t48/tags/rel_0_6_1_beta/ |
143 |
Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle |
arniml |
7184d 00h |
/t48/tags/rel_0_6_1_beta/ |
142 |
deassert rd_q, wr_q and prog_q at end of XTAL3 |
arniml |
7184d 00h |
/t48/tags/rel_0_6_1_beta/ |
141 |
disable external memory to avoid conflicts with outl a, bus |
arniml |
7184d 00h |
/t48/tags/rel_0_6_1_beta/ |
140 |
remove tAW sanity check
conflicts with OUTL A, BUS |
arniml |
7184d 00h |
/t48/tags/rel_0_6_1_beta/ |
139 |
add bug
P1 constantly in push-pull mode in t8048 |
arniml |
7185d 10h |
/t48/tags/rel_0_6_1_beta/ |
138 |
Fix for:
P1 constantly in push-pull mode in t8048 |
arniml |
7185d 10h |
/t48/tags/rel_0_6_1_beta/ |
137 |
add link to COMPILE_LIST |
arniml |
7222d 23h |
/t48/tags/rel_0_6_1_beta/ |
136 |
initial check-in |
arniml |
7222d 23h |
/t48/tags/rel_0_6_1_beta/ |
135 |
add bug
PSENn Timing |
arniml |
7227d 09h |
/t48/tags/rel_0_6_1_beta/ |
134 |
Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR. |
arniml |
7227d 19h |
/t48/tags/rel_0_6_1_beta/ |
133 |
add checks for PSEN |
arniml |
7227d 19h |
/t48/tags/rel_0_6_1_beta/ |