URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] - Rev 188

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
188	move check for int_pending_s into ea_i_='0' branch this fixes a glitch on PCH when an interrutp occurs during external program memory fetch	arniml	6922d 03h	/t48/tags/rel_0_6_1_beta/
187	Fix bug reports: "Target address of JMP to Program Memory Bank 1 corrupted by interrupt" "Return address of CALL to Program Memory Bank 1 corrupted by interrupt" int_in_progress_o was active one cycle before int_pending_o is asserted. this confused the mb multiplexer which determines the state of the memory bank selection flag	arniml	6922d 03h	/t48/tags/rel_0_6_1_beta/
186	update to version 0.2	arniml	6923d 05h	/t48/tags/rel_0_6_1_beta/
185	initial check-in	arniml	6928d 03h	/t48/tags/rel_0_6_1_beta/
184	initial check-in	arniml	6928d 04h	/t48/tags/rel_0_6_1_beta/
183	fix missing assignment to outclock	arniml	6928d 07h	/t48/tags/rel_0_6_1_beta/
182	intermediate version	arniml	7008d 05h	/t48/tags/rel_0_6_1_beta/
181	fix typo	arniml	7008d 08h	/t48/tags/rel_0_6_1_beta/
180	introduce prefix 't48_' for wb_master entity and configuration	arniml	7016d 14h	/t48/tags/rel_0_6_1_beta/
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	7016d 14h	/t48/tags/rel_0_6_1_beta/
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	7018d 02h	/t48/tags/rel_0_6_1_beta/
177	Implement db_dir_o glitch-safe	arniml	7018d 02h	/t48/tags/rel_0_6_1_beta/
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	7018d 02h	/t48/tags/rel_0_6_1_beta/
175	add bug report "MSB of Program Counter changed upon PC increment"	arniml	7019d 05h	/t48/tags/rel_0_6_1_beta/
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	7019d 05h	/t48/tags/rel_0_6_1_beta/
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	7019d 05h	/t48/tags/rel_0_6_1_beta/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7048d 02h	/t48/tags/rel_0_6_1_beta/
171	remove obsolete output stack_high_o	arniml	7049d 02h	/t48/tags/rel_0_6_1_beta/
170	intermediate update	arniml	7050d 08h	/t48/tags/rel_0_6_1_beta/
169	initial check-in	arniml	7050d 14h	/t48/tags/rel_0_6_1_beta/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] - Rev 188

Filtering Options