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[/] [t48/] [tags/] [rel_0_6_1_beta/] - Rev 210

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210 entity changes for P2 low impedance marker issue arniml 6872d 22h /t48/tags/rel_0_6_1_beta/
209 entity changes for P2 low impedance issue arniml 6872d 22h /t48/tags/rel_0_6_1_beta/
208 wire signals for P2 low impeddance marker issue arniml 6872d 22h /t48/tags/rel_0_6_1_beta/
207 entity changes for P2 low impedance trigger issue arniml 6872d 22h /t48/tags/rel_0_6_1_beta/
206 * change low impedance markers for P2
separate marker for low and high part
* p2_o output is also registered to prevent combinational
output to pads
arniml 6872d 22h /t48/tags/rel_0_6_1_beta/
205 operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3 arniml 6872d 22h /t48/tags/rel_0_6_1_beta/
204 * suppress p2_output_pch_o when p2_output_exp is active
* wire xtal_i to interrupt module
arniml 6872d 22h /t48/tags/rel_0_6_1_beta/
203 * shift assertion of ALE and PROG to xtal3
* correct change of revision 1.8
arniml 6872d 22h /t48/tags/rel_0_6_1_beta/
202 fix address assignment arniml 6872d 22h /t48/tags/rel_0_6_1_beta/
201 split low impedance markers for P2 arniml 6872d 22h /t48/tags/rel_0_6_1_beta/
200 add check for
tCP: Port Control Setup to PROG'
arniml 6872d 22h /t48/tags/rel_0_6_1_beta/
199 initial check-in arniml 6872d 22h /t48/tags/rel_0_6_1_beta/
198 fix package dependencies arniml 6873d 03h /t48/tags/rel_0_6_1_beta/
197 preliminary version 0.3 arniml 6874d 06h /t48/tags/rel_0_6_1_beta/
196 update to version 0.3 arniml 6874d 06h /t48/tags/rel_0_6_1_beta/
195 Suppress assertion of bus_read_bus_s when interrupt is pending.
This should fix bug report
"PROBLEM WHEN INT AND JMP"
arniml 6874d 09h /t48/tags/rel_0_6_1_beta/
194 initial check-in arniml 6874d 09h /t48/tags/rel_0_6_1_beta/
193 iManual arniml 6889d 11h /t48/tags/rel_0_6_1_beta/
192 update list for Wishbone toplevel arniml 6889d 22h /t48/tags/rel_0_6_1_beta/
191 preliminary version 0.2 arniml 6890d 01h /t48/tags/rel_0_6_1_beta/

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