URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_1_beta/] [bench/] - Rev 103

Rev	Log message	Author	Age	Path
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7347d 12h	/t48/tags/rel_0_6_1_beta/bench/
83	connect if_timing to P2 output of T48	arniml	7369d 06h	/t48/tags/rel_0_6_1_beta/bench/
82	check expander timings	arniml	7369d 06h	/t48/tags/rel_0_6_1_beta/bench/
81	initial check-in	arniml	7369d 10h	/t48/tags/rel_0_6_1_beta/bench/
80	added if_timing	arniml	7369d 10h	/t48/tags/rel_0_6_1_beta/bench/
68	connect T0 and T1 to P1	arniml	7376d 08h	/t48/tags/rel_0_6_1_beta/bench/
67	initial check-in	arniml	7376d 08h	/t48/tags/rel_0_6_1_beta/bench/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7380d 06h	/t48/tags/rel_0_6_1_beta/bench/
33	rename pX_limp to pX_low_imp	arniml	7396d 07h	/t48/tags/rel_0_6_1_beta/bench/
30	connect prog_n_o	arniml	7397d 05h	/t48/tags/rel_0_6_1_beta/bench/
19	enhance simulation result string	arniml	7399d 04h	/t48/tags/rel_0_6_1_beta/bench/
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7401d 03h	/t48/tags/rel_0_6_1_beta/bench/
8	initial check-in	arniml	7401d 05h	/t48/tags/rel_0_6_1_beta/bench/